1. Field of the Invention
The present invention relates to a method of forming a metal gate in a semiconductor device. More particularly, the present invention relates to a method of forming a metal gate having a line width that is less than a resolution limit of a conventional photolithography system.
2. Description of the Related Art
As semiconductor devices continue to become more highly integrated, the pattern size, that is the minimum line width of line patterns that can be formed on the substrate, continues to become more reduced. At the same time, semiconductor devices such as memory devices, non-memory devices, or logic devices, all require a high-performance transistor that is capable of operating with high speed at a relatively low voltage, which further requires the line width of the pattern to be reduced.
In general, a gate electrode of a transistor comprises a polysilicon material. However, use of polysilicon is limited in that the line width of the gate electrode cannot be reduced beyond the resolution limit in a conventional photolithography system. For this reason, a slant etching process or a sidewall recessing process is performed for forming a transistor having a line width that is less than the resolution limit of the photolithography process. However, the slant etching process or the sidewall recessing process is disadvantageous in that the line width of a pattern to be formed is not controlled with sufficient precision, and the pattern profile formed by the slant etching process or the sidewall recessing process is rarely satisfactory.
In addition, when polysilicon material is used for forming an MOS transistor irrespective of whether the transistor is a PMOS or an NMOS-type transistor, hole or electron mobility is changed due to stress induced by the polysilicon layer, thus electrical characteristics of the semiconductor device are altered in accordance with the mobility change. Further, there is also a problem in that operation speed of the transistor is reduced since the electrical resistance of the polysilicon is relatively high.
Accordingly, metal materials have been widely utilized in place of the polysilicon material for forming a gate electrode of a semiconductor device. For example, U.S. Pat. No. 6,236,094 discloses that the metal is stacked on the gate electrode comprising polysilicon for reducing the electrical resistance thereof, and U.S. Pat. No. 6,033,963 discloses that a gate oxide layer and a metal gate are formed after a trench is formed adjacent to a portion of the substrate at which a gate electrode is to be formed. The approaches discussed in the above U.S. patents are advantageous in that the electrical resistance of the transistor can be reduced, however, they are still limited in that the gate electrode has a minimum line width that is less than the resolution limit of the photolithography process.